Here is a question that has occupied me for longer than I am willing to admit, mostly because the answer turns out to matter in contexts that have nothing to do with paddle sports: is ping pong mini tennis, or is tennis mini ping pong?
the field theory
If you hold tennis as the reference object, then ping pong is obviously the mini version. Take a tennis court, 78 feet long with painted lines and a net down the middle, and shrink everything: smaller court, smaller net, smaller ball, moved indoors onto a table. The field has been miniaturized, and ping pong is tennis compressed in space. If you flip the reference and hold ping pong as the baseline, then tennis is the mini version too, except it is the player that has been miniaturized rather than the field. The table stays the same size. The ball stays the same size relative to the game. The person playing is now operating at a scale where they are genuinely tiny compared to the court, not bigger, just given more room, and seen from the ball’s perspective, a tennis player is a distant, stumbling thing on the far side of an enormous plain.
Both framings are correct, and neither is more correct than the other. Ping pong is mini tennis because the field shrank. Tennis is also mini ping pong because the player shrank, relatively speaking. The word “mini” is doing all the work here and it means nothing on its own, because it is always relative to a reference frame that someone else chose and did not bother to disclose.
this is a chip industry problem
The semiconductor industry has a version of this argument running continuously, and the stakes are considerably higher than whether you play indoors.
To fix the terms: the court has two dimensions. Die area is the physical size of the silicon. Process node is how many transistors fit per square millimeter of that area. Together they set the total transistor budget. A bigger die gives you more court even at the same node; a smaller node gives you more transistors per unit of court. The player is the architecture built from that budget: the pipeline design, the instruction set, the IPC, and every other decision about what to do with the transistors the court provides.
The relationship that matters is this: with die area held constant, when a process node shrinks from 14nm to 7nm, roughly four times as many transistors fit in the same space. The court did not change in size. The player grew. This was the deal Moore’s Law always promised: keep the court the same, and the player gets bigger with every node generation, essentially for free. In practice, die area is rarely constant across chip generations, and when the die grows the court grows and the player gets more budget from that too, and when the die shrinks the court gets smaller even if the node stays the same. Both dimensions move the court independently, and the press release will tell you about whichever one moved in the flattering direction.
One case stands apart before the historical examples. When Intel’s 10nm process launched in 2019 and turned out to match TSMC’s 7nm in transistor density, the story is not about courts or players at all. It is about who gets to define what the sport is called. Intel and TSMC were both building courts and filling them with players; the dispute was about whose ruler you use to measure the courts. If TSMC’s naming convention is the reference sport, then Intel labeling their equivalently-dense process as 10nm means Intel is calling a ping pong table a tennis court: TSMC’s table is the standard, and Intel’s label implies their court is larger than it actually is. If Intel’s naming convention is the reference, then TSMC calling that same density 7nm means TSMC is labeling their court as smaller than the Intel standard would call it. Neither company was lying about the physical transistors; they were using different sports as the reference, and each looked misleading from the other’s perspective, which is a strange situation to be in when you are supposedly describing an objective physical measurement.
the perspective problem is older than the marketing problem
IBM POWER5 to POWER6. POWER5 ran on 130nm with a die of roughly 389mm² and about 276 million transistors. POWER6 moved to 65nm with a die of roughly 341mm² and about 790 million transistors. The die shrank slightly, but the node halved in feature size, and the net effect was roughly a tripling of the transistor count. The court changed in a direction that should have grown the player substantially. IBM spent that budget on pipeline depth to reach 4.7 GHz: more stages meant each stage was simpler and could switch faster, so the clock went up. But each clock cycle completed less work, IPC fell relative to POWER5, and the cost of a branch misprediction or pipeline stall rose sharply. For floating-point workloads that could keep the pipeline fed, throughput was competitive. For general-purpose and branch-heavy code, effective instructions completed per second went backward. The court gave the player three times the transistors, and the player used them to become slower at the fundamental task of completing the game. Tennis is mini ping pong: the player’s useful effectiveness per clock shrank relative to its predecessor, on a court that had given it every reason to improve.
Intel Pentium III to Pentium 4 Prescott. The Pentium III Tualatin ran on 130nm with a die around 80mm² and about 45 million transistors. The transition to Pentium 4 did not proceed cleanly: the first revision, Willamette, launched on a coarser 180nm node with a die of around 217mm², meaning the court actually got bigger and less dense simultaneously, and transistor count stayed roughly flat at 42 million despite the larger die because the density dropped. By Prescott on 90nm with 112mm² and 125 million transistors, the node had recovered and the transistor count had tripled relative to the original Pentium III. The player was owed substantially more capability than the Pentium III delivered. Netburst spent it all on a 31-stage pipeline to chase clock speeds to 3.8 GHz, which is the kind of decision that looks great on a spec sheet and reveals itself slowly as you notice your new machine running hotter, louder, and somehow not faster than the one it replaced. Prescott consumed far more power and in most general-purpose workloads delivered lower IPC and equivalent or worse throughput than what it replaced. The player received three times the transistors and used everything to become worse at retiring instructions. Tennis is mini ping pong again: the player regressed on a court that had given it every reason to be substantially better.
AMD Bulldozer to Zen. Bulldozer’s 8-core chip ran on 32nm with a die around 315mm² and roughly 1.2 billion transistors. Zen’s 8-core chip ran on 14nm with a die around 213mm² and roughly 4.8 billion transistors. The die shrank by about 32 percent, taking some court away, while the node dropped from 32nm to 14nm, more than compensating with density. The net effect was a 4x increase in transistors despite the smaller physical die. Where the previous two examples show a player squandering a larger budget, AMD used the 4x transistor count to improve IPC by roughly 52 percent over Bulldozer. Single-threaded throughput became competitive with Intel for the first time in years, which is a sentence that would have seemed implausible for most of the preceding decade, and multi-threaded throughput per watt improved dramatically. Ping pong is mini tennis: AMD put their player on a smaller table, and the player became substantially better at the game than it ever was on the larger one.
what “mini” is hiding
Court changes and player changes are independent axes that the industry routinely conflates, and the conflation is not always accidental. Court changes are physical: die area and process node. Shrink the die and you reduce cost, heat, and total transistor budget. Shrink the node and more transistors fit per unit of area, growing the player budget within the same or smaller court. Both are measurable, and both have direct consequences on what the player can do.
Player changes are architectural: IPC, throughput, and power per operation. These are decisions about what to do with the transistor budget the court provides. The same budget can be spent on a deep pipeline that raises clock speed while degrading IPC, on wide execution units that retire more instructions per cycle, or on a larger cache that reduces memory stalls. The court sets the budget. The player decides what to buy with it, and the announcement will describe whichever purchase sounds most impressive in a headline.
The recurring trick is to point at a court change and imply a player improvement, or to report one dimension of player change while hiding regression in another. A node shrink grew your transistor budget but your IPC fell? Report the clock speed. Your die grew and you filled it with a deeper pipeline? Report the gigahertz. Your node name got smaller but your density did not? Report the node name. The answer to whether ping pong is mini tennis or tennis is mini ping pong depends entirely on what you decided to hold fixed, and the people writing the press releases know this, and they are very good at choosing.